In a typical static random access memory (SRAM) there is a period defined by an external write signal during which the logic state of a data input signal is written into a memory location defined by an address. There is typically a specification defining how long the write signal must remain active following a change in the data input signal. This is commonly known as data valid to write high (DVWH). There is also a data-hold specification which specifies how long the data input signal must be valid following the termination of write which is commonly phrased as write high to data don't care (WHDX). As access times get lower, both of these specifications must also get lower. As these specifications get lower there is a potential conflict with read access time because before a read can be performed the memory must first recover from the write.
The need for write recovery is addressed in U.S. Pat. No. 4,110,840, Abe et al, which teaches that there is problem associated with a read following a write. A write forces a selected bit line pair and a data line pair to a full rail or nearly full rail separation. During a write, one bit line of a selected bit line pair is driven to a voltage at or near one power supply terminal, and the other bit line of the selected bit line pair is driven to a voltage at or near the other power supply terminal. One problem of this full rail separation was that if there was a change in word line selection at the same time as a change from a write to read transition, a newly selected cell would be coupled to a bit line pair having full rail separation which could, due to the large bit line capacitance, reverse the data in the newly selected cell. The solution was to precharge the low bit line in response to switching from the write to read mode. This was achieved using the data lines. This approach is commonly used. Another approach has relied on address transition to perform the needed precharge and/or equalization of bit lines and data lines. These approaches have utility but are not fully satisfactory for providing the desired DVWH specification in a SRAM which has a self-timed write. A self-timed write is used in very high speed applications, such as when ECL and MOS are combined to make an SRAM.